/*
 * Copyright (c) 2019 Tang Haifeng <pengren.mcu@qq.com>
 *
 * Loongson2 SOC Clock Register Definitions.
 *
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef __ASM_MACH_LOONGSON2_SOC_REGS_CLK_H
#define __ASM_MACH_LOONGSON2_SOC_REGS_CLK_H

#define LS2X_CLK_REG(x) \
		((void __iomem *)PHYS_TO_UNCACHED(LS2X_PLL_BASE + (x)))

#define LS2X_NODE_PLL_L		LS2X_CLK_REG(0x00)
#define LS2X_NODE_PLL_H		LS2X_CLK_REG(0x04)
#define LS2X_DDR_PLL_L		LS2X_CLK_REG(0x08)
#define LS2X_DDR_PLL_H		LS2X_CLK_REG(0x0c)
#define LS2X_SOC_PLL_L		LS2X_CLK_REG(0x10)
#define LS2X_SOC_PLL_H		LS2X_CLK_REG(0x14)
#define LS2X_PIX0_PLL_L		LS2X_CLK_REG(0x18)
#define LS2X_PIX0_PLL_H		LS2X_CLK_REG(0x1c)
#define LS2X_PIX1_PLL_L		LS2X_CLK_REG(0x20)
#define LS2X_PIX1_PLL_H		LS2X_CLK_REG(0x24)
#define LS2X_FREQ_SCALE		LS2X_CLK_REG(0x28)

#define NODE_L1DIV_OUT_SHIFT		24
#define NODE_L1DIV_LOOPC_SHIFT		16
#define NODE_L1DIV_REF_SHIFT		8

#define NODE_L1DIV_OUT_WIDTH		6
#define NODE_L1DIV_LOOPC_WIDTH		8
#define NODE_L1DIV_REF_WIDTH		6

#define NODE_L1DIV_OUT_MARK			0x3f
#define NODE_L1DIV_LOOPC_MARK		0xff
#define NODE_L1DIV_REF_MARK			0x3f


#define DDR_L2DIV_OUT_HDA_SHIFT		8
#define DDR_L2DIV_OUT_NET_SHIFT		0
#define DDR_L1DIV_OUT_SHIFT			24
#define DDR_L1DIV_LOOPC_SHIFT		16
#define DDR_L1DIV_REF_SHIFT			8

#define DDR_L2DIV_OUT_HDA_WIDTH		6
#define DDR_L2DIV_OUT_NET_WIDTH		6
#define DDR_L1DIV_OUT_WIDTH			6
#define DDR_L1DIV_LOOPC_WIDTH		8
#define DDR_L1DIV_REF_WIDTH			6

#define DDR_L2DIV_OUT_HDA_MARK	0x3f
#define DDR_L2DIV_OUT_NET_MARK	0x3f
#define DDR_L1DIV_OUT_MARK			0x3f
#define DDR_L1DIV_LOOPC_MARK		0xff
#define DDR_L1DIV_REF_MARK			0x3f


#define SOC_L2DIV_OUT_GMAC_SHIFT	8
#define SOC_L2DIV_OUT_SB_SHIFT		0
#define SOC_L1DIV_OUT_SHIFT			24
#define SOC_L1DIV_LOOPC_SHIFT		16
#define SOC_L1DIV_REF_SHIFT			8

#define SOC_L2DIV_OUT_GMAC_WIDTH	6
#define SOC_L2DIV_OUT_SB_WIDTH		6
#define SOC_L1DIV_OUT_WIDTH			6
#define SOC_L1DIV_LOOPC_WIDTH		8
#define SOC_L1DIV_REF_WIDTH			6

#define SOC_L2DIV_OUT_GMAC_MARK		0x3f
#define SOC_L2DIV_OUT_SB_MARK		0x3f
#define SOC_L1DIV_OUT_MARK			0x3f
#define SOC_L1DIV_LOOPC_MARK		0xff
#define SOC_L1DIV_REF_MARK			0x3f


#define PIX_L1DIV_OUT_SHIFT		24
#define PIX_L1DIV_LOOPC_SHIFT		16
#define PIX_L1DIV_REF_SHIFT		8

#define PIX_L1DIV_OUT_WIDTH		6
#define PIX_L1DIV_LOOPC_WIDTH		8
#define PIX_L1DIV_REF_WIDTH		6

#define PIX_L1DIV_OUT_MARK			0x3f
#define PIX_L1DIV_LOOPC_MARK		0xff
#define PIX_L1DIV_REF_MARK			0x3f

#define FREQSCALE_LSU_SHIFT		27
#define FREQSCALE_PRINT_SHIFT		24
#define FREQSCALE_APB_SHIFT		20
#define FREQSCALE_USB_SHIFT		16
#define FREQSCALE_SATA_SHIFT		12
#define FREQSCALE_SB_SHIFT		8
#define FREQSCALE_GPU_SHIFT		4
#define FREQSCALE_NODE_SHIFT		0

#define FREQSCALE_LSU_MARK			0x7
#define FREQSCALE_PRINT_MARK			0x7
#define FREQSCALE_APB_MARK			0x7
#define FREQSCALE_USB_MARK			0x7
#define FREQSCALE_SATA_MARK		0x7
#define FREQSCALE_SB_MARK		0x7
#define FREQSCALE_GPU_MARK		0x7
#define FREQSCALE_NODE_MARK		0x7

#endif /* __ASM_MACH_LOONGSON2_SOC_REGS_CLK_H */
